In recent years much effort has been directed toward perfecting a method of integrating bipolar and complimentary metal oxide semiconductor (CMOS) technologies on a single wafer. The ability to combine CMOS with bipolar processes in a single ("BiCMOS") process is extremely desirable for high performance circuits. For example, CMOS transistors are inherently low power devices with large noise margins that can achieve a high packing density. Meanwhile, bipolar transistors provide advantages in switching speed and current drive. Bipolar transistors are also characterized by high transconductance which is well suited for driving capacitive loads.
One of the difficulties presented in integrating an MOS device with a bipolar device in the same circuit is that the fabrication steps required to form each of the separate devices often differ radically. That is, the steps used to fabricate a bipolar device are vastly different from the steps required to fabricate a CMOS or an MOS device. As a result, conventional processes are often lengthy and complicated, using a large number of masking operations and numerous thermal cycles.
Another basic limitation to prior art processes has to do with the nature of optical lithography and its affect on the attainable circuit density. In the widely used technique of projection printing, an image of the patterns on the mask is projected onto a resist coated wafer. Upon the exposure of an individual chip site the wafer is moved or stepped on an interferometrically controlled XY table to the next site and the process is repeated. Using state-of-the-art optics, projection printing (also frequently referred to as direct-step-on-wafer or step-and-repeat) systems are capable of producing sub-micron resolutions.
However, this high level of resolution does not come without a corresponding trade-off. The trade-off in this case is the limited depth of focus over which the image quality is maintained. For projection printing, the depth of the focus is approximated by the equation EQU d.f. (depth of focus)=.lambda./2(NA).sup.2
where NA is the numerical aperture of the projection optics and .lambda. is the exposure wavelength. Thus, high resolution (very large numerical aperture) is achieved at the expense of a very shallow depth of focus.
In other words, the ability to print a highly dense circuit layout, having minimal device sizes and structures, is especially dependant on the existence of a highly planar surface on which geometric shapes from a mask may be transferred. Unfortunately, the requirement of a highly planar surface is completely at odds with orthodox methods of forming a semiconductor circuit in a silicon substrate.
Traditionally, in fabricating an integrated circuit the silicon substrate layer is first subject to oxidation. Openings are etched in the oxide, and then impurities are introduced or implanted into the substrate. Next, the silicon surface is either reoxidized or subjected to depositions of polysilicon, CVD oxide, silicon nitride, etc. The result of these successive processing steps (e.g., oxidation, etching, implantation, reoxidation) are large steps or incongruities running across the surface of the wafer. Obviously, over the course of the entire process these steps or incongruities lead to a non-uniform, non-planar wafer surface. Consequently, the ability to maintain high image quality (due to the depth of focus problems described above) is substantially degraded in prior methods.
One way in which practitioners have attempted to minimize this problem is to planarize the surface of the wafer by reflowing a boron-phosphosilicate glass across the wafer surface prior to contact mask. The surface is then aggressively planarized using sophisticated etchants when the metalization steps are reached. Despite these attempts to replanarize the wafer surface in the back-end processing steps, the lack of planarization in the front-end processing steps (i.e., those steps leading up to the contact mask step) has already taken its toll on the devices. The inability to pattern compact and high-resolution device structures brings about low-density, low-performance circuits. Hence, past semiconductor processes, and particularly BiCMOS processes, have not been able to take full advantage of the high numerical aperture (i.e., resolution) which modern optical equipment can produce due to the depth of focus problem. The critical importance of maintaining planarization throughout each and every processing step is therefore appreciated.
As will be seen, the presently invented BiCMOS process maintains an extremely high level of planarization throughout all of the processing steps using a novel technique known as "waffelization". When combined with a number of additional novel processing features (each of which is believed to be separately inventive in its own right) the disclosed BiCMOS process is capable of producing device dimensions and circuit densities well beyond the limits of the prior art. For example, using the presently invented process it is possible to produce gate widths of 0.5 microns or less on MOS-type devices and emitter widths of roughly 0.2 microns for bipolar transistors. Consequently, it is contemplated that a 6-transistor memory cell may easily be fabricated within an area of about 3.0.times.4.8 microns--or a total dimension of approximately 14.4 square microns. This is about the size of a via contact opening in many prior processes.
In addition to achieving high circuit densities and high device performance through planarization of the wafer surface, the invented BiCMOS process is also characterized by its simplicity, reliability, its self-aligning nature, and the overall design flexibility provided--both from a circuit design perspective as well as an applications specific viewpoint.
Other prior art known to Applicant includes U.S. Pat. No. 4,727,046 of Tuntasood et al.; U.S. Pat. No. 4,826,783 of Choi et al.; and U.S. Pat. No. 4,816,423 of Havemann.